As a step toward ultimate low-power computing, this book introduces normally-off computing, which involves inactive components of computer systems being aggressively powered off with the help of new non-volatile memories (NVMs). Because the energy consumption of modern information devices strongly depends on both hardware and software, co-design and co-optimization of hardware and software are indispensable to improve energy efficiency. The book discusses various topics including (1) details of low-power technologies including power gating, (2) characteristics of several new-generation NVMs, (3) normally-off computing architecture, (4) important technologies for implementing normally-off computing, (5) three practical implementations: healthcare, mobile information devices, and sensor network systems for smart city applications, and (6) related research and development. Bridging computing methodology and emerging memory devices, the book is designed for both hardware and software designers, engineers, and developers as comprehensive material for understanding normally-off computing. About the Editors Hiroshi Nakamura is a professor in the Department of Information Physics and Computing at The University of Tokyo. He is also the director of the Information Technology Center at The University of Tokyo. He received the Ph.D. degree in electrical engineering from The University of Tokyo in 1990. His research interests are ultra-low-power VLSI design, power-aware computing systems, and high-performance parallel computer systems. He has been an executive committee member of the IEEE/ACM International Symposium on Low-Power Electronics and Design (ISLPED) since 2012 and a steering committee member of the IEEE Non-Volatile Memory Systems and Applications Symposium (NVMSA) since 2014. He is leading the Normally-Off Computing project supported by NEDO (New Energy and Industrial Technology Development Organization) and METI (Ministry of Economy, Trade and Industry) of Japan. He is a senior member of IEEE and ACM. Takashi Nakada is an assistant professor in the Department of Information Physics and Computing at The University of Tokyo. He received the Ph.D. degree in electronic and information engineering from Toyohashi University of Technology in 2007. His research interests include power-aware computing systems, processor architecture, and related simulation technologies. He has been a program committee member of the IEEE International Conference on Computer Design (ICCD) since 2015 and was a registration chair of the 10th IEEE/ACM International Symposium on Networks-on-Chip (NOCS2016). He is a member of IEEE and ACM.
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